FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics

Publication Name : IEICE Electronics Express 12 (16), 20150450-20150450, 2015

Citation : 4

Date : 2015


Publication URL
https://scholar.google.com/scholar?q=+intitle:"FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics"