FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on vedic mathematics

Publication Name : IEICE Electronics Express

DOI : 10.1587/elex.12.20150450

Date : 21 July 2015


Publication URL
https://www.scopus.com/record/display.uri?eid=2-s2.0-84940118814&origin=resultslist&sort=plf-f
Type
Journal
ISSN
13492543
Volume
12
Page