Cascaded Multilevel Inverter with Minimum Number of Conducting Switches and Using Capacitor Compensation

paper presents the design and implementation of an improved cascaded multilevel inverter topology with symmetrical DC source with minimum number of switching and minimum conducting switches during operation The proposes new topology is designed as a stand-alone system and simulated using resistive and inductive loads. One drawback of the others topology is the occurrence of voltage surges in the inductive load due to the emf effect. By using a capacitor on the dc bus as a compensation, the emf effect can be minimized. The size of the capacitor used should be proportional to the reactive power of the load. The proposed new topology is more efficient in use of switching components, conducting switches and can overcome inductive loads. It can generate 21 level with 14 switches needed and only 3 conducting switches during operation. The value of THDv and THDi from the proposed new topology is 3.76% and 0.93%, it varies depending on the value of the load received.